1. Field of the Invention
The present invention relates generally to electronic design techniques used for designing integrated circuits, and in particular to methods and mechanisms for optimizing the design flow used to process integrated circuit designs.
2. Description of the Related Art
The design of complex and high performance integrated circuits requires a considerable investment of time and cost. Typically, designers of integrated circuits follow multiple steps and use multiple software design tools to create a fabricated chip. Initially, the designer may use a hardware description language (HDL), such as Verilog or VHDL, to describe the original design. Then, the design may be synthesized by a synthesis tool into the logic needed to implement the desired logical functionality of the design. This may be followed by the generation of a description at the transistor and circuit component level. The next step may be the layout step where the circuit elements are placed within the overall circuit. Then, following the layout step, the wiring between the placed circuit elements may be arranged and routed.
When designing an integrated circuit, this design flow may be traversed hundreds of times or more from start to finish. After each pass through the design flow, simulations may be run on the placed and routed design to evaluate its performance. The design may need to meet various predetermined performance goals, including desired clock speed and power consumption. Additionally, any flaws or undesired behavior may be corrected by making changes to the design and then making another pass through the design flow.
As the design is nearing completion, typically only minor changes are made to the design for each iteration. However, a drastically different placement and routing of the design may be produced by the tools of the design flow even for small changes to the design. As such, the results of the implementation tools of a slightly different version of the design do not leverage the results of the previous version of the design. Therefore, there may not be any significant improvement in the quality of results or execution time from one design version to another. This may be undesirable when the design is fairly convergent and performing close to the desired result. Such unpredictability in the place and route construction and quality of results can have a negative impact on tight time to market schedules.